Reversible Evolvable Networks: A Reversible Evolvable Boolean Network Architecture and Methodology to Overcome the Heat Generation Problem in Molecular Scale Brain Building

Today’s irreversible computing style, in which bits of information are routinely wiped out (e.g. a NAND gate has 2 input bits, and only 1 output bit), cannot continue. If Moore's Law remains valid until 2020, as many commentators think, then the heat generated in molecular scale circuits that Moore's Law will provide, would be so intense that they will explode [Hall 1992]. To avoid such heat generation problems, it has been known since the early 1970s [Bennet 1973] that the secret to ``heatless computation'' is to compute reversibly, i.e. not to destroy bits, by sending in the input bit-string through a computer built from reversible logic gates (e.g. Fredkin gates [Fredkin et al 1982], to record the output answer and then send the output bit-string backwards through the computer to obtain the original input bit-string. This reversible style of computing takes twice as long, but does not destroy bits, hence does not generate heat. (Landauer's principle states that “the heat generated from irreversible computing is derived from the destruction of bits of information” [Landauer 1961]). This paper proposes a reversible evolvable Boolean network architecture and methodology which, it is hoped, will stimulate the evolvable hardware and evolvable neural network research communities to devote more effort towards solving this problem, which can only accentuate as Moore's Law continues to bite.